1. Field of the Invention
The present invention relates to a semiconductor device that includes a transistor, JFET, and thyristor, more particularly to a monolithic IC (Integrated circuit) with built-in high withstand voltage switching elements.
2. Description of the Prior Art
Many bipolar IC semiconductor devices are fabricated in an epitaxial layer grown in a surface of a semiconductor substrate. This epitaxial layer is reverse in conductivity type to the substrate, with a pn junction electrically isolating the epitaxial layer and substrate from each other. In the epitaxial layer, isolation walls of the same conductivity type as the substrate and/or isolation regions are comprised of an insulating substance and are provided to form individual circuit element regions and wells electrically isolated from the surrounding areas. Since each well is electrically isolated by a pn junction or the like at the bottom of the well (interface between the epitaxial layer and substrate) and at the side walls, the emitter, base and collector electrodes of a bipolar junction transistor are all fabricated at the top of the well (the surface of epitaxial layer). With such electrode layout and as carriers flow from the emitter to the collector these carriers necessarily move in a horizontal direction (parallel to the surface of epitaxial layer). If the well is formed as a region of high resistivity with a low impurity concentration is provided in the horizontal direction, therefore, the collector series resistance, etc. becomes high. Such high collector series resistance results in an increase in the RC time constant, lowering the response speed of the transistor. For this reason, many bipolar ICs are designed so that each well used for the fabrication of a transistor has an embedded region of high impurity concentration (subcollector region) in the surface of the substrate or in proximity to the interface between the substrate and epitaxial layer, which is of the same conductivity type as the epitaxial layer and electrically continuous to such layer. The above subcollector region of high impurity concentration (low conductivity) spreads in the horizontal direction in the well, substantially reducing the resistivity of the well in such direction and thereby allowing a faster response, etc. of the transistor.
For the bipolar junction transistor with such embedded subcollector region, however, the emitter-collector withstand voltage is determined by the base-collector withstand voltage, namely, primarily by the impurity concentration and thickness (base-subcollector distance) of an epitaxial region sandwiched between the base region and the subcollector region below the emitter region. The configuration (for example, the curvature) of the base region also affects the withstand voltage.
In a silicon region doped with impurities at a concentration of 10.sup.18 cm.sup.-3 or under, the breakdown that occurs there is primarily of the avalanche type. As the factor of causing the avalanche breakdown, a critical electrical field intensity, say, 10.sup.5 to 10.sup.6 V/cm is ordinarily assumed. As such critical electric field intensity is exceeded at some point in a transistor, there occurs a breakdown. Accordingly, to achieve a high withstand voltage, a large potential drop must be attained without exceeding the critical electric field intensity. For this end, it is effective to reduce the impurity concentration in the region of epitaxial layer between the base and subcollector regions and increase the thickness of such layer. However, thicker growth of the epitaxial layer of low impurity concentration has difficulties in the process control, etc. and tends to decrease the production yield. Further, since the epitaxial layer is ordinarily formed to a uniform thickness in the semiconductor wafer, the thickness of epitaxial layer increases also in other regions. Beside, it then becomes necessary to increase the depth and width of isolation walls. The above method will thus lead to a lower circuit integration by a more complicated process. For this reason, the thickness of epitaxial layer is limited. As a result, bipolar transistors that have been fabricated for practical applications have withstand voltages of up to about 60 V.
In view of the above circumstances, the proposed a high withstand voltage semiconductor device solves the problems mentioned above. The proposed semiconductor device has bipolar transistors fabricated as mentioned above and is characterized by the selection of the impurity concentration in the epitaxial layer (collector region) and the distance between the substrate and base region such as the collector voltage increases with a low level of signal voltage applied to the base region, the depletion layers extending from the semiconductor substrate and base region, respectively, grow in size large enough to cause the pinch-off condition before there appears any breakdown between collector and emitter regions. FIG. 1 is an example of such semiconductor device (in individual semiconductor regions, hatching of cross-sectional areas is omitted for easier understanding; the same applies to drawings hereinafter referred to). Referring to the switching npn bipolar transistor BTr of the above example, the embedded region of low resistivity as mentioned above is omitted with the n.sup.- inner collector region 21 sandwiched between the p base region 3 and p.sup.- substrate 1. The inner collector region 21 is set to such impurity concentration n.sup.- and thickness t that, as a voltage higher than a given level Vc is applied to the collector 21, the depletion layers 20 and 22 extend from the base region 3 and substrate 1, respectively, and come in contact as shown. Assuming that both the base region 3 and substrate 1 are grounded, the above requirement can be satisfied only if the width Wd of both depletion layers roughly conforms to the following inequality: ##EQU1## where .epsilon..sub.o is the dielectric constant of vacuum, Ks the relative dielectric constant, q the charge on the electron, and n the impurity concentration. In case of silicon (Ks.apprxeq.12), assuming n=10.sup.15 cm.sup.-3 and t=6 .mu.m, therefore, the voltage Vc required to bring the depletion layers in contact is about 8 V. With n=10.sup.16 cm.sup.-3 and the same t, the depletion layers come in contact at Vc.apprxeq.50 V.
The depletion layer is, in other words, a region where there is a potential gradient. As a continuous depletion layer is formed between the inner collector region 21 underlying the base region 3 and the collector's charge collection region 5 (this corresponds to the drain of JFET), therefore, the highest potential in the inner collector region 21 is naturally lower than the potential in the collector's charge collection region 5. Accordingly, the sum of the voltage of inner collector region 21 and the voltage drop from such inner collector region 21 to the collector's charge collection region 5 is the collector voltage of this compound transistor. Even when the voltage of the inner collector region 21 is limited to around the ordinary level, a high potential drop in the depletion layer gives a high collector voltage. This means that the application of a high voltage to the collector, namely, region 5, will cause no avalanche breakdown below the emitter region.
It is noted that if the distance "Wc" between the base region 3 and collector's charge collection region 5 or the distance "d" between the collector's charge collection region 5 and substrate 1 is short, the avalanche breakdown occurs readily there. Accordingly, Wc must not be less than t/2. The proper values of Wc and d can be estimated from the desirable withstand voltage. In FIG. 1, the p.sup.+ isolation walls 23, surface oxide film 24, emitter electrode 25, base electrode 26, collector electrode 27 and field electrode 28 are fabricated.
Adjustments of the specific resistance of epitaxial layer 2 to about 3 ohm-cm (n.sup.- .apprxeq.1.5.times.10.sup.15 cm.sup.-3), the distance t between the base region 3 and substrate 1 to approx. 7 .mu.m, and the base diffusion depth to approx. 1.6 .mu.m (surface concentration of approx. 10.sup.18 cm.sup.-3 and base width of approx. 5 .mu.m at surface) were found to give a base-collector withstand voltage BVceo higher than 210 V. This is a substantial improvement when compared to a BVcbo around 60 V achieved by the prior art. Horizontally aligned subregions of emitter region 4, base region 3, collector regions 2, 5, subregions which are primarily involved in determination of the withstand voltage characteristics, do not practically constitute any bipolar transistor (.beta.&lt;0.1), so BVceo.apprxeq.BVcbo. It is thus noted that an even larger difference is expected, when the comparison is made to the ordinary BVceo value.
The JFET that uses the above collector's charge collection region 5 for drain is, a bulk type FET cascaded to the above BTr. In this FET, the inner collector region 21 serves as the source while the substrate 1 and base region 3 constitute the gate. In such a FET, even when the drain voltage changes, the source is not affected much, supplying almost a constant current. After the depletion layers join to establish the pinch-off condition, the potential of the inner collector region 21 is not much affected by changes in the collector voltage Vc. The channel length of the above pseudo-FET can be assumed to be the distance between the aforementioned emitter-base and base-collector junctions (hereinafter abbreviated EB and BC junctions, respectively) in the horizontal direction. In the above example, the channel length was larger than 5 .mu.m. The primary factor of causing the avalanche breakdown is the relation between the p base (gate) region 3 (or the p.sup.- substrate 1) and n.sup.- epitaxial layer 2. With the ordinary impurity concentration and the ratio of p/n.sup.- being higher than 100, the withstand voltage is primarily determined both by the impurity concentration of epitaxial layer 2 and the length of horizontal region between the base region 3 and collector's charge collection region 5.
In the compound transistor of FIG. 1 the bulk JFET and BTr are fabricated in cascaded connection in such a manner that the pinch-off voltage Vp of the former is lower than the BVceo and is characterized by a high withstand voltage greater than 200 V. However, further studies revealed such a weak point of the above compound transistor and the omission of the aforementioned embedded region of low resistivity increases the on for saturation voltage.